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Ingenieur Design Asic Rtl Digital Ic Designer Confirme H F

Freelanceonsite5+ yrs📍 Rousset, 🇫🇷 France🗣 English

Senior ASIC RTL design engineer for secure processor development.

Tech stack
SystemVerilogVerilogVHDLPythonC++RISC-VFPGA
Rate
€400-600/day
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Found at a specialist agency · listed 21 July 2026 · InsideJobs links you to the original posting.