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Ingenieur Verification Rtl Uvm Senior F H

Permanenthybrid5+ yrs📍 Paris, 🇫🇷 France🗣 English

Senior RTL verification engineer for advanced SoC design and validation tools.

Tech stack
SystemVerilogVerilogVHDLPythonUVMCadenceSynopsysSiemens
Rate
Not stated by the agency
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Found at a specialist agency · listed 25 July 2026 · InsideJobs links you to the original posting.